1. Field of the Invention
The present invention relates to a switched capacitor circuit which operates in response to a two-phase high frequency clock signal to synthesize an equivalent resistor.
2. Description of the Related Art
A prior art switched capacitor circuit as shown in FIG. 1 comprises a first sampling switch S1 of single-pole-double-throw (SPDT) type connected to an input terminal 100 for coupling it to a circuit node 101 in response to a first phase .phi.1 of a two-phase high frequency clock signal and coupling the node 101 to ground in response to the second phase .phi.2 of the clock signal. A second sampling switch S2 of the SPDT type is connected to a circuit node 103 for coupling it to ground in response to phase .phi.1 and coupling it, in response to phase .phi.2, to the inverting input of an operational amplifier 106, which functions as the energy supply source for the switched capacitor circuit. Between the circuit nodes 101 and 103 is provided a variable sampling capacitor circuit SC1 comprising a capacitor 102 with value C.sub.s which is in shunt with a plurality of gain control switches D.sub.i and sampling capacitors C.sub.i respectively connected to switches D.sub.i, where i=1, 2, . . . 8. The least to most significant bits of an eight-bit binary signal are applied respectively to the gain control switches D.sub.1 to D.sub.8 for coupling the associated capacitors in shunt with the fixed capacitor 102 in response to a bit "1". The capacitance of each of the switched capacitors C.sub.1 is equal 2.sup.i .times.C.sub.o where C.sub.o is the capacitance unit. The circuit node 103 is further connected through a transfer capacitor 104 to a third sampling switch S3 of the SPDT type. Third sampling switch S3 is responsive to phase .phi.1 for coupling the transfer capacitor 104 to ground for discharging it and responsive to phase .phi.2 for coupling it to the output terminal 107 to which the output of operational amplifier 106 is connected. A feedback capacitor 105 is connected between the inverting input of operational amplifier 106 and output terminal 107 to stabilize the operational amplifier when the inverting input is disconnected from circuit node 103. Since the gain (V.sub.out /V.sub.in) of the switched capacitor circuit is given by the ratio of the total capacitance of the variable sampling capacitor circuit SC1 to the capacitance C.sub.t of transfer capacitor 104, it can be adjusted to one of 256 capacitance ratios (i.e., C.sub.s /C.sub.t, (C.sub.s +C.sub.o)/C.sub.t, (C.sub.s +2C.sub.o)/C.sub.t, (C.sub.s +3C.sub.o)/C.sub.t, . . . , (C.sub.s +255C.sub.o)/C.sub.t) in response to an 8-bit gain control signal, using 255 capacitance units.
From the power savings standpoint of the operational amplifier 106 it is desirable to reduce the total number of capacitance units as well as to reduce the value of the capacitance unit itself. However, the precision of the capacitance ratio tends to decrease as the value of the capacitance unit C.sub.o decreases due to the process limitations imposed by the integrated circuit technique. Since the capacitance unit value C.sub.o cannot be reduced below what is obtainable by the integrated circuit technology, it is important to reduce the total number of capacitance units.
To reduce the total number of capacitance units C.sub.o to 131 units, as well as the total of the capacitances of sampling capacitor and transfer capacitor to 1/64 of FIG. 1, a variable sampling capacitor circuit SC2 of what is known as the ladder or T-type structure is shown in FIG. 2. According to this prior art, each of the switched capacitor circuits formed by gain control switches D.sub.k (where k-1, 2, 3, . . . 6) includes a series of capacitors C.sub.k1 and C.sub.k3 and a capacitor C.sub.k2 connected across the node between capacitors C.sub.k1 and C.sub.k3 and ground. All capacitors C.sub.k1 and C.sub.k3 except for C.sub.63 has unit capacitance value C.sub.o, while capacitor C.sub.63 has twice the unit capacitance value, and all capacitors C.sub.k2 except for capacitor C.sub.62 has a capacitance equal to (2.sup.(7-k) -2)C.sub.o and the capacitor C.sub.62 is of the unit value C.sub.o. The values of capacitors 102 and 104 are reduced to C.sub.s /64 and C.sub.t /64, respectively. After charging the capacitors C.sub.k1, C.sub.k2 and C.sub.k3, the charge stored on capacitor C.sub.k3 is transferred to the transfer capacitor 104. Since the amount of energies discharged by the gain control sampling capacitors is given by V.sub.in .times.C.sub.k1 .times.C.sub.k3 /(C.sub.k1 +C.sub.k2 +C.sub.k3), each of the capacitor networks connected to switches D.sub.1 to D.sub.6 has an equivalent capacitance C.sub.k1 .times.C.sub.k3 /(C.sub.k1 +C.sub.k2 +C.sub.k3) ranging from C.sub.o /64 to C.sub.o /2. A further prior art sampling capacitor circuit SC3 which is known as the .pi. structure reduces the total number of capacitance units C.sub.o to 65 units as shown in FIG. 3. According to this .pi. structure each of the capacitor networks associated with switches D.sub.j (where j=1 and 2) is formed by a series of unit-value capacitors C.sub.j1, C.sub.j3, C.sub.j5 and grounded capacitors C.sub.j2 and C.sub.j4 respectively coupled to the node between capacitors C.sub.j1 and C.sub.j3 and the node between C.sub.j3 and C.sub.j5. The values of the grounded capacitors C.sub.12 and C.sub.14 are 3C.sub.o and 11C.sub.o, respectively, and those of the grounded capacitors C.sub.22 and C.sub.24 are C.sub.o and 9C.sub.o, respectively. The quantity of the charges transferred from the gain control sampling capacitors is given by V.sub.in .times.C.sub.j1 .times.C.sub.j3 .times.C.sub.j5 /{(C.sub.j1 +C.sub.j2)(C.sub.j3 +C.sub.j4 +C.sub.j5)+C.sub.j3 (C.sub.j4 +C.sub.j5)}. The equivalent capacitances of the capacitor networks with switches D.sub.1 and D.sub.2 are equal to C.sub.o /64 and C.sub.o /32, respectively.
However, there is still a need to decrease the number of capacitance units for each of the T- and .pi.-type of sampling capacitor networks.